Sony CXD5602 User Manual page 44

with functional blocks. A variety of processors can dynamically select multiple usable clock source, and use most
suitable clock frequency optimized for the operating conditions by using divider circuit architecture.
The functions of clock and reset of the CXD5602 are described below.

Clock Source
The CXD5602 has following clocks.

RTC Clock:

is 32.768 kHz real time clock input from outside chip

is assumed to be input as the RTC clock from external the RTC oscillator or the PMIC containing
the RTC oscillator

can be used as clock for the RTC counter circuit incorporated in the chip, as system clock in
operation with low power, and as clock of sensing circuit in operation with low power such as the
SCU, as well.

RCOSC (RC Oscillator) Clock:

is 8.192 MHz incorporated ring oscillator

becomes 8.192 MHz by being calibrated with RTC clock

incorporates POR system

XOSC (X'tal Oscillator) Clock:

X'tal 26MHz

can be used as CPU operation clock, in addition, can be supplied to SYSPLL and RFPLL as
reference clock

SYSPLL Clock:

incorporates low power PLL which realizes high CPU operation frequency without any input of
high speed clock from outside.

Following frequencies can be selected as SYSPLL clock according to the combination of suitable
X'tal frequency variation and the division ratio of the PLL.

Under high speed oscillation setting: 195.000 MHz

Under usual speed oscillation setting: 156.000 MHz

RFPLL Clock (Clock generated in PWD_GNSS):

is provided from the PLL (RFPLL) included in the PWD_GNSS for the RF block

Following frequencies can be selected as RFPLL clock according to the suitable X'tal frequency
variation.

GPS/Beidou mode: 196.416 MHz

Reset Source
The following reset functions are prepared for whole chip reset.

Power On reset (POR) issued from the external PMIC

The POR issued from the POR circuit incorporated in the RCOSC

The above POR can be enabled or disabled with external input.
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CXD5602 User Manual