Sony CXD5602 User Manual page 161

*Supported frequencies: 26 MHz
The XOSC can be used as the processor's operation clock and is also supplied as the reference clock to the
SYSPLL and RF.
3.5.3.2.1 Register Descriptions
Table Clock and Reset (Clock Reset Generator)-52 shows the control registers related to the XOSC block.
Table Clock and Reset (Clock Reset Generator)-52 XOSC Block Status Register
Address Register
Name
0x04100580 XOSC_C
TRL
Bit Field Type
Name
Reserved RW
IXO_LV_LOCLK_E RW
N
IXO_LV_PLLCLK_E RW
N
IXO_LV_SENCLK_ RW
EN
IXO_LV_LOGICLK_ RW
EN
Reserved RW
－161/1010－
Bit Initial Description
Value
[31:20] 0 Reserved
[19] 0 Indicated as ANA(5) in
Reset (Clock Reset Generator)-34
Clock Enable for GNSS
0: Clock supplied, 1: Clock stopped
[18] 0
Indicated as ANA(4) in
Reset (Clock Reset Generator)-34
Clock Enable for SYSPLL block
0: Clock supplied, 1: Clock stopped
[17] 0
Indicated as ANA(3) in
Reset (Clock Reset Generator)-34
Clock Enable for HPADC
0: Clock supplied, 1: Clock stopped
[16] 0
Indicated as ANA(2) in
Reset (Clock Reset Generator)-34
Clock Enable for each function block
0: Clock supplied, 1: Clock stopped
[15:0] 0 Reserved
CXD5602 User Manual
Figure Clock and
Figure Clock and
Figure Clock and
Figure Clock and