Sony CXD5602 User Manual page 49

PWD_PMU
Application Domain
APP
PWD_APP_DSP
Application Processor
(Cortex-M4 x 6)
32b Multi-Layer AHB
SRAM
(1.5MB)
PWD_APP
PWD_CORE
GNSS Domain
PWD_GNSS
GNSS
GNSS DSP
(Cortex-M4)
32b Multi-Layer AHB
SRAM ROM
(640KB)
(64KB)
32b Multi-Layer AHB
GNSS Reciever
RF BB ITP
The following describes the functions of each power domain.
Application Domain

PWD_APP

All components of Application Domain

Including 1.5 MByte SRAM in Application memory and Application Multi-layer Bus

PWD_APP_DSP

Application processors

DSP block

ADMAC

PWD_APP_SUB

Connectivity, Storage I/F and Camera, Display Interface in Application Domain

PWD_APP_AUD
Crypto
ADMAC
(AES)
System and IOP Domain
PWD_SYSIOP
SYSIOP
debugger I/F
ITM
System and
I/O Processor
(Cortex-M0+)
32b Multi-Layer AHB
SRAM
Sync
Up/Down Up/Down
(256KB)
PWD_SYSIOP_SUB
ROM
SPI Flash
Controller
(128KB)
Figure Power Management-5 CXD5602 Power Domain
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Imaging / 2D
S S U
2D
A
P P
CIS
R
Graphi
IDMAC
I I
I/F
T
cs
PWD_APP_SUB 4 5
2
APB
AHB
Sync
32b Multi-Layer AHB
PWD_APP_AUD
Async
FREQDISC
Sync
SYDMAC HDMAC
32b Multi-Layer AHB
HOSTIFC
Async
APB
S I U S I
Crypto
SYSUB
A
P 2 P 2
R
DMAC (Clefia)
I C I C
T
0 2 2 3
1
CXD5602 User Manual
Storage/Connectivity
eMMC USB SDIO
Audio Codec
Audio
DSP
Power Management,
Clock,
Reset
RTC1 RTC0
BackUp
SRAM
SDMAC
Sync
(64KB)
Sensor Domain
Async Async
APB APB
PWD_SCU
U L H S I I P
Sequencer
FIFO
A P P W
P 2 2
R A A M
SRAM
(40KB)
I C C
T D D ×
(1KB)
3 0 1
0 C C 4
I2S0
I2S1
PDM
CRG
RTC Clock
RCOSC
XOSC
SysPLL
PMU
I2C4
IOCTRL
GPIO
INTCTL
e-fuse
SCU
Sensor
Engine