Sony CXD5602 User Manual page 8

CXD5602 User Manual
Figure SCU (Sensor Control Unit)-69 Sequencer Overall Image .......................................................................... 278
Figure SCU (Sensor Control Unit)-70 Sequencer Process Flow (Example) ......................................................... 278
Figure SCU (Sensor Control Unit)-71 Overall Data Flow (excluding Data Duplication Function) ...................... 279
Figure SCU (Sensor Control Unit)-72 Startup Control ......................................................................................... 280
Figure SCU (Sensor Control Unit)-73 External Bus Transaction Generation ....................................................... 281
Figure SCU (Sensor Control Unit)-74 External Data Capture .............................................................................. 282
Figure SCU (Sensor Control Unit)-75 Sensor Data Flow when Capturing External Data .................................... 283
Figure SCU (Sensor Control Unit)-76 Data Normalization (Example) ................................................................. 284
Figure SCU (Sensor Control Unit)-77 Data Stacked in the FIFO (Image) ............................................................ 285
Figure SCU (Sensor Control Unit)-78 Sequencer Data Flow ................................................................................ 292
Figure SCU (Sensor Control Unit)-79 Sequencer Completed ............................................................................... 294
Figure SCU (Sensor Control Unit)-80 Sequencer Suspended ............................................................................... 294
Figure SCU (Sensor Control Unit)-81 MATH_PROC Parameter Change (Example) .......................................... 295
Figure SCU (Sensor Control Unit)-82 Error Notification (Example) .................................................................... 297
Figure SCU (Sensor Control Unit)-83 DMA Handshake Signal Connections ...................................................... 299
Figure SCU (Sensor Control Unit)-84 PWM Output Mode using ADC Timing as a Reference .......................... 303
Figure SCU (Sensor Control Unit)-85 ADC Data Capture Mode using the PWM Output Timing as a Reference
........................................................................................................................................................................... 306
Figure SCU (Sensor Control Unit)-86 Processing Block Overview ...................................................................... 354
Figure SCU (Sensor Control Unit)-87 Filter Overview ......................................................................................... 356
Figure SCU (Sensor Control Unit)-88 Excess Detection Overview ...................................................................... 392
Figure SCU (Sensor Control Unit)-89 I2C Master Control (Example) ................................................................. 860
Figure SCU (Sensor Control Unit)-90 Basic Startup Timing ................................................................................ 861
Figure SCU (Sensor Control Unit)-91 Delay at Start (Example) .......................................................................... 861
Figure SCU (Sensor Control Unit)-92 Time Stamp Fluctuation by the Presence/Absence of HPADC Execution866
Figure SCU (Sensor Control Unit)-93 Counter Basic Operation .......................................................................... 868
Figure SCU (Sensor Control Unit)-94 1 One-to-One Connection (Example) ....................................................... 869
Figure SCU (Sensor Control Unit)-95 One-to-N Connection (Example) .............................................................. 869
Figure SPI-96 SPI0 Clock and Reset System ........................................................................................................ 876
Figure SPI-97 SPI3 Clock and Reset System ........................................................................................................ 879
Figure SPI-98 SPI4 Clock and Reset System ........................................................................................................ 880
Figure SPI-99 SPI5 Clock and Reset System ........................................................................................................ 882
Figure UART-100 UART1 Clock and Reset System ............................................................................................ 885
Figure UART-101 UART2 Clock and Reset System ............................................................................................ 887
Figure APP-102 Application Domain Clock System ............................................................................................ 896
Figure APP-103 Application Domain Reset System ............................................................................................. 897
Figure APP-104 APP_DSP Block Diagram .......................................................................................................... 907
Figure APP-105 WDTRES Connection ................................................................................................................ 914
Figure APP-106 Address Map ............................................................................................................................... 918
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