Sony CXD5602 User Manual page 35

Two channels 10 bit high performance ADC
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Multi-GNSS Controller
® ®
Arm Cortex -M4 processor with FPU 32 bit RISC
Operating frequency up to 98.208 MHz
64 KByte ROM
640 KByte SRAM
CORDIC engine for GNSS support
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Multi-GNSS receiver
GPS (L1 C/A)
GLONASS (L1OF)
QZSS (L1 C/A, L1 SAIF)
SBAS (L1 C/A)
WAAS, EGNOS, MSAS
BeiDou (B1)
Galileo (E1 CBOC)
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Configurable I/O
I2C/SPI/GPIO Interfaces
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Debug
Serial wire debug (SWD), Embedded Trace Macrocell
UART supported
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CXD5602 User Manual