Sony CXD5602 User Manual page 909

Memory
16 SRAM with protection feature
Clock Reset
17 Clock Reset Generator
Other
18 Interrupt Output
3.13.4.3 Register List
Address Register Name
0x0E002040 PID
DSP_SLEEPING
0x0E002044
0x0E002048 WD_TIM_RES
0x0E010000 BUS_ERROR0
0x0E010004 BUS_ERROR1
0x0E010008 BUS_ERROR2
0x0E012004 ACNV_P0_DST_{0-7}
|
0x0E012020
0x0E012024 ACNV_P1_DST_{0-7}
|
0x0E012040
0x0E012044 ACNV_P2_DST_{0-7}
|
0x0E012060
0x0E012064 ACNV_P3_DST_{0-7}
|
0x0E012080
0x0E012084 ACNV_P4_DST_{0-7}
|
0x0E0120A0
0x0E0120A4 ACNV_P5_DST_{0-7}
|
0x0E0120C0
The SRAM module consists of 128 KByte Logic Tile units, holding access control
function for each tile, and AHB slave interface.
The Clock Reset Generator generates clocks and resets required for the sub block in
the Application Domain.
For the main purpose of debugging, this function outputs interrupts which occur in
the APP_DSP block for the processors in the SYSIOP block and the GNSS block.
Table APP-751 APP_DSP Register List
Type Description
RO Processor ID
RO SLEEPING Signal Monitor
RO Watchdog Timer Status
WO BUS ERROR Clear Register
RO BUS ERROR Cause Register (Error Type)
RO BUS ERROR Cause Register (Master ID)
RW Address Converter (ADSP0)
RW Address Converter (ADSP1)
RW Address Converter (ADSP2)
RW Address Converter (ADSP3)
RW Address Converter (ADSP4)
RW Address Converter (ADSP5)
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CXD5602 User Manual
Initial Value
-
0
0
0
0
0
-
-
-
-
-
-