3.5.5
Power Domain Reset
The reset of each power domain can be controlled by the registers excluding some domains.
When releasing a reset, first perform ON control of the corresponding power domain, and then release the reset.
To enable a reset, first perform OFF control of the corresponding power domain, and then enable the reset.
Table Clock and Reset (Clock Reset Generator)-57 shows the relation between each power domain and the reset
control registers.
Table Clock and Reset (Clock Reset Generator)-57 Power Domain and the Reset Control Registers
Power Domain
PWD_PMU
PWD_CORE
PWD_SYSIOP
PWD_SYSIOP_SUB
PWD_SCU
PWD_APP
PWD_APP_DSP
PWD_APP_SUB
PWD_APP_AUD
PWD_GNSS_ITP
PWD_GNSS
Register
None
Reset is automatically released at start up
PWD_RESET0.PWD_SYSIOP_SUB
PWD_RESET0.PWD_SCU
PWD_RESET0.PWD_APP
Enables/releases reset of domain layers lower than
the PWD_APP
PWD_RESET0.PWD_GNSS_ITP
PWD_RESET0.PWD_GNSS
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CXD5602 User Manual