Sony CXD5602 User Manual page 958

0x000
LPADC0 FIFO Read
0x004
LPADC1 FIFO Read
0x008
LPADC2 FIFO Read
0x00C
LPADC3 FIFO Read
0x080
HPADC0 FIFO Read
0x084
HPADC1 FIFO Read
3.21.4 Power Supply Control
The LPADC and the HPADC belong to power domain called PWD_SCU. Inside PWD_SCU, as lower level
power supply domains, there are module areas for power supply control shown below. Power supply control
registers for such areas are held in the TOPREG.
Target for Address
Power Supply Offset
Control
LPADC 0x0004
HPADC
For control details, refer to Section of the SCU Control Sequence described in Chapter of the SCU (3.9).
Figure ADC-119 Memory Map inside the ADCIF
Table ADC-772 Power Supply Information
Bit Bit Name
(TOPREG)
[29] WEN_LPADC
[13] LPADC
[28] WEN_HPADC
[12] HPADC
－958/1010－
0x000
FIFO Read Port
0x200
LPADC
0x260
HPADC Common
0x2A0
HPADC0
0x300
HPADC1
0x320
for Test
0x3FF
Description
LPADC Power supply control Write
Enable
0: Disable 1: Enable
LPADC Power supply control
0: OFF 1: ON
HPADC Power supply control Write
Enable
0: Disable 1: Enable
HPADC Power supply control
0: OFF 1: ON
CXD5602 User Manual