Sony CXD5602 User Manual page 165

3.5.4.1.2 Clock Enable
Table Clock and Reset (Clock Reset Generator)-56 shows the status registers of clock Enable (clock
supplied/clock stopped).
Table Clock and Reset (Clock Reset Generator)-56 Clock Enable Status Registers
Address Register
Name
0x041004C0 PMU_CO
RE_CKE
N
Bit Field Type
Name
Reserved RO
BKMEM RW
HCLK_KAKI RW
RTC_PCLK RW
PMU_RTC_PCLK RW
－165/1010－
Bit Initial Description
Value
[31:4] 0 Reserved
[3] 1
Indicated as CG(3) in
Reset (Clock Reset Generator)-34
Clock Enable for BackUpSRAM
1: Clock supplied
0: Clock stopped
[2] 0
Indicated as CG(2) in
Reset (Clock Reset Generator)-34
Clock Enable for Crypto (Clefia)
[1] 1
Indicated as CG(1) in
Reset (Clock Reset Generator)-34
Clock Enable for I2C4
[0] 1
Indicated as CG(0) in
Reset (Clock Reset Generator)-34
Clock Enable for I2C4 register IF
CXD5602 User Manual
Figure Clock and
Figure Clock and
Figure Clock and
Figure Clock and