Modes Of Operation Overview; Sdram Interface; Sdram Signals - Intel PXA27 Series Design Manual

6.5

Modes of Operation Overview

Refer to the following subsections for description of the specific operations and signals including
example schematics, timing diagrams and layout notes for the PXA27x processor memory
controller supported memories:
•
Part II: Section 6.5.1, "SDRAM Interface"
•
Part II: Section 6.5.2, "Flash Memory Interface (Asynchronous/Synchronous)"
•
Part II: Section 6.5.3, "ROM Interface"
•
Part II: Section 6.5.5, "Variable Latency Input/Output (VLIO) Interface"
•
Part II: Section 6.5.6, "PC Card (PCMCIA) Interface"
•
Part II: Section 6.5.7, "Alternate Bus Master Interface"
6.5.1

SDRAM Interface

The PXA27x processor supports an SDRAM interface at a maximum frequency of 100 MHz. The
SDRAM interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is
allocated 64 Mbytes of the internal memory map. However, the actual size of each partition is
dependent on the particular SDRAM configuration used. The four partitions are divided into two
partition pairs: 0/1 pair and the 2/3 pair. Both partitions within a pair must be identical in size and
configuration. However, the two pairs can be different.
Example: Partition 0 and Partition 1. The 0/1 pair is 100-MHz SDRAM on a 32-bit data bus
whereas the 2/3 pair is 66-MHz SDRAM on a 16-bit data bus.
6.5.1.1

SDRAM Signals

See Table 6-5
Table 6-5. SDRAM I/O Signals (Sheet 1 of 2)
Signal Name
SDCLK<2:1>
SDCKE
nSDCS<3:0>
MA<24:10>
MD<31:0>
DQM<3:0>
®
Intel PXA27x Processor Design Guide
for the list of signals required to interface to SDRAM memory devices.
Direction Polarity
Output Active High
Output Active High
Output Active Low
Output NA
Bidirectional NA
Output Active High
System Memory Interface
Description
Output clocks to clock external memory
SDCLK1 is for SDRAM partitions 0 and 1
SDCLK2 is for SDRAM partitions 2 and 3
Output clock enable signals for external memory
SDCKE is for all SDRAM memory partitions
Chips selects for SDRAM
Output address to all memory types
Bidirectional data for all memory types
Data byte mask control
DQM<0> corresponds to MD<7:0>
DQM<1> corresponds to MD<15:8>
DQM<2> corresponds to MD<23:16>
DQM<3> corresponds to MD<31:24>
0 = Do not mask out corresponding byte
1 = Mask out corresponding byte
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