Block Diagram - Intel PXA27 Series Design Manual

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25.3

Block Diagram

See
Figure 25-1
controller on a bit-by-bit basis. Each register in the illustration represents a bit related to a specific
interrupt. This logic is copied 31 times for the additional 31 possible interrupts represented.
Figure 25-1
Figure 25-1. Interrupt Controller Block Diagram
Interrupt Level
Register
ICCR[DIM] = 0b0 &
Processor in IDLE state
Interrupt Mask
Register
Interrupt Source
Bit
Interrupt Pending
Register
IRQ Interrupt
Pending Register
FIQ Interrupt
Pending Register
Highest Priority
Register
Interrupt Priority
Register
®
Intel
PXA27x Processor Family Design Guide
for illustration of how the interrupt registers are implemented in the interrupt
shows all other qualified interrupt bits.
All Other
Qualified
Interrupt Bits
31
31
32
32
Peripheral Priority
Processor
INT_001_P2
Interrupt Interface
FIQ Interrupt to
Processor
IRQ Interrupt to
Processor
II:25-3

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