Layout Notes; Active Color, 16-Bit Per Pixel Mode; Active Color 12-Bit Per Pixel Display Typical Connection - Intel PXA27 Series Design Manual

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LCD Interface
Figure 7-6. Active Color 12-bit per pixel Display Typical Connection
7.5.6.3

Layout Notes

Refer to
Section 7.4, "Layout Notes,"
7.5.7

Active Color, 16-bit per pixel Mode

An active color display does not send dithered data to the panel. The lines driven represent the
digital value of the pixel being transmitted. A single pixel is transmitted per clock cycle. The 16
bits of data describe the intensity level of red, green, and blue for each pixel. Typically, the 16-bit
data is formatted as five bits for red, six bits for green, and five bits for blue, but the format varies
by display and is controlled by the software writing to the frame buffer. Refer to the display
documentation to ensure the correct PXA27x processor LCD data lines are connected to the correct
LCD panel data lines.
Note: The LCD controller of the PXA27x processor includes the ability to use logical overlays for
simplified software control of multiple planes (overlays) of image data. While this is essentially a
software-related feature, the implementation of the overlays for 16-bit per pixel operation impacts
the way in which signals are connected between the PXA27x processor and LCD panel. Set
LCCR0[LDDALT] to avoid any issues associated with the implementation of the overlays. Refer
to the description of the LCD Controller Control Register 0 in Section 7.5, "LCD Control
Registers," of the Intel
II:7-16
LDD<0>
LDD<1>
LDD<2>
LDD<3>
LDD<4> MSB of blue
LDD<5>
LDD<6>
LDD<7>
LDD<8>
LDD<9>
LDD<10> MSB of green
LDD<11>
LDD<12>
LDD<13>
LDD<14>
LDD<15> MSB of red
L_PCLK_WR
L_LCLK_A0
L_FCLK_RD
L_BIAS
for layout notes and considerations.
®
PXA27x Processor Family Developers Manual for more information.
Intel
B0
B1
B2
B3
G0
G1
G2
G3
R0
R1
R2
R3
CLOCK
HORIZ. SYNC
VERT. SYNC
DATA ENABLE
®
PXA27x Processor Family Design Guide

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