Features - Intel PXA27 Series Design Manual

JTAG Debug
Figure 26-1. Test Access Port (TAP) Block Diagram
TDI
TMS
TCK
nTRST
26.2

Features

The boundary-scan interface complies with IEEE Standards 1149.1-1990, IEEE Standards
1149.1a-1993, and IEEE Standard Test Access Port and Boundary-Scan Architecture, with support
for:
•
Board-level boundary-scan connectivity testing
•
Connection to software debugging tools through the JTAG interface
•
In-system programming of programmable memory and logic devices on the PCB
Refer to the IEEE 1149.1 standard for an explanation of the terms used in this section and a
complete description of the TAP-controller states.
II:26-2
Instruction
Register (7 bits)
Boundary-Scan Register
TAP
Controller
Control And Clock Signals
Test Data Registers
Bypass Register (1 bit)
Device ID Register (32 bits)
Data-Specific Registers
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Intel PXA27x Processor Family Design Guide
TDO