Sdram Memory Block Diagram - Intel PXA27 Series Design Manual

6.5.1.2

SDRAM Memory Block Diagram

See Figure 6-5
bank SDRAM devices for a total of 48 Mbytes. Refer to
Signal Mapping," on page II:
Figure 6-5. SDRAM Memory System Example
nSDCS<3:0>
nSDRAS, nSDCAS, nWE,
SDCLK<2:1>
MA<24:10>
MD<31:0>
DQM<3:0>
®
Intel PXA27x Processor Design Guide
for example of a wiring diagram showing a system using 1 Mword x 16-bit x 4-
6-13, to determine the individual SDRAM component address.
SDCKE
4Mx16
SDRAM
0
nCS
nRAS
nCAS
nWE
CKE
1
CLK
addr<11:0>
BA<1:0>
0
DQML
1
DQMH
15:0
DQ<15:0>
4Mx16
SDRAM
0
nCS
nRAS
nCAS
nWE
CKE
1
CLK
21:10
addr<11:0>
23:22
BA<1:0>
2
DQML
3
DQMH
31:16
DQ<15:0>
System Memory Interface
Section 6.5.1.3.2, "SDRAM Address
4Mx16
SDRAM
1
nCS
nRAS
nCAS
nWE
CKE
1
CLK
addr<11:0>
BA<1:0>
0
DQML
1
DQMH
15:0
DQ<15:0>
4Mx16
SDRAM
1
nCS
nRAS
nCAS
nWE
CKE
1
CLK
21:10
addr<11:0>
23:22
BA<1:0>
2
DQML
3
DQMH
31:16
DQ<15:0>
4Mx16
SDRAM
2
nCS
nRAS
nCAS
nWE
CKE
2
CLK
addr<11:0>
BA<1:0>
0
DQML
1
DQMH
15:0
DQ<15:0>
4Mx16
SDRAM
2
nCS
nRAS
nCAS
nWE
CKE
2
CLK
21:10
addr<11:0>
23:22
BA<1:0>
2
DQML
3
DQMH
31:16
DQ<15:0>
II:6-11