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Summary of Contents for Intel Pentium II
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Page 1: Pentium Ii Processor
® Pentium II Processor – Low-Power Module at 266 MHz Memory Bus Simulation Methodology Application Note June 1999 Order Number: 273217-002... - Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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Page 3: Table Of Contents
Flight Time (Rising Edge)..................12 Flight Time (Falling Edge) ................... 13 Flight Time Measurement (With Ringing)............15 Tables Related Intel Documents ..................5 Fast, Slow, and Worst-Case Signal Quality Corner Interconnect Models ..... 7 Low-Power Module Memory Interface Pin Loading..........9 Simulation Conditions..................10 Signal Quality Criteria..................14... -
Page 5: Introduction
II Processor – Low-Power Module datasheet (order number 273256). Intel 440BX AGPset refers to both the 82443 BX Host Bridge/Controller and the 82371EB PCI ® ISA IDE Xcelerator. A complete description of this chipset is located in both the Intel... -
Page 6: Simulation Prerequisites
Simulation Block Diagram Figure 1 shows the simulation block diagram for the Low-Power Module/DIMM memory interface. The Pentium II Processor Mobile Module MMC-2 I/O Buffer Model describes the interconnect characteristics between the Low-Power Module 400-pin connector, and the 82443BX Host Bridge/Controller. -
Page 7: Details Of The Electrical Interconnect Models
Low-Power Module Memory Bus Simulation Methodology Figure 1. Simulation Model Components TL-4 TL-1 TL-2 TL-3 TL-5 82443BX 400-pin DIMM TL-6 IBIS Connector Connector SDRAM IBIS A6429-01 Details of the Electrical Interconnect Models This section provides detailed information on the electrical interconnect models used for the simulation. -
Page 8: Simulation Conditions
Low-Power Module Memory Bus Simulation Methodology Figure 2, shows the Pi-element network model used for the 400-pin module connector. Figure 2. 400-pin Connector Package Model R = 0.01 Ohms L = 3.5 nH 0.5 pF 0.5 pF AA6430-01 Figure 3 shows the Pi-element network model used for the DIMM connector. Figure 3. -
Page 9: Dimm Connection
Low-Power Module Memory Bus Simulation Methodology Figure 4. DIMM Connection DIMM 1 DIMM 0 Closest Connector Farthest Connector CS_A[3:2]#, CS_A[3:2]# /S1/S0,/S3/S2 CS_A[1:0]#, CS_A[1:0]# /RAS SRAS_A# /CAS SCAS_A# DQM_A[7:0]# WE_A# A[13:0] MAB[12:11,9:0]#, MAB[13,10] DQ[63:0] MD[63:0] CB[7:0] MECC[7:0] CK[3:0] DIMM_CLK[3:0] DIMM_CLK[7:4] CKE_[1:0] CKE_[3:2] SMB_CLK SMB_DATA... -
Page 10: Simulation Conditions
Low-Power Module Memory Bus Simulation Methodology Table 4 lists the Low-Power Module/DIMM condition used in the simulation. Each driver/receiver pair of the memory signal with the heaviest/lightest pin load is simulated with these conditions. The first four entries of the table are used for slow corner (setup) simulations in conjunction with heaviest receiver pin loads of the driver/receiver signal pair. -
Page 11: Flight Time And Signal Quality Definitions
Low-Power Module Memory Bus Simulation Methodology Flight Time and Signal Quality Definitions Procedure 1: Determining Flight Time The flight time of the Low-Power Module memory interface is measured from the reference waveform, which is generated by driving a 0 pf load to the receiving pin, as shown in Figure 5. Figure 5. -
Page 12: Flight Time Determination For Setup Time
Low-Power Module Memory Bus Simulation Methodology 6.1.1 Flight Time Determination for Setup Time The maximum flight time measurement is used to determine the setup time of a memory signal. Both the rising and falling edges should be considered. Figure 6 shows the determination of maximum flight time for the rising edge of a memory signal. -
Page 13: Hold Time
Low-Power Module Memory Bus Simulation Methodology Figure 7 shows the determination of flight time for the falling edge of a signal. Figure 7. Flight Time (Falling Edge) 2.0 V 1 V/ns 1 V/ns 1.4 V 0.8 V 0.8 V A6435-01 The flight time of the falling edge is determined between the driver and receiver at 1.4 V. -
Page 14: Procedure 2: Signal Quality
Low-Power Module Memory Bus Simulation Methodology Procedure 2: Signal Quality Signal quality is simulated using the fast corner models because the fast edge rates will induce the worst case overshoot and ringback. Overshoot is that part of the signal that transitions above V below V when measured at the receiver pin. -
Page 15: Flight Time Measurement (With Ringing)
Low-Power Module Memory Bus Simulation Methodology Figure 8. Flight Time Measurement (With Ringing) 3.3 V 2.0 V 1.4 V Ledge 0.8 V A6434-01 Application Note...
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