Test Access Port (Tap) Controller - Intel PXA27 Series Design Manual

JTAG Debug
26.4.5

Test Access Port (TAP) Controller

The TAP controller is a 16-state, synchronous, finite state machine that controls the sequence of
test logic operations. The TAP is controlled using a bus master that is an automatic test equipment
or a programmable logic device that interfaces with the TAP. The TAP controller changes state only
in response to power-up or a rising edge of TCK. The value of the TMS input signal at a rising edge
of TCK controls the sequence of state changes. The TAP controller is automatically initialized on
power up. It is also initialized by applying a high signal level on the TMS input for five TCK
periods.
The following subsections describe the behavior of the TAP controller and other test logic in each
controller state. See
controller. For more information on the TAP states and the public instructions, refer to the IEEE
1149.1 standard.
Figure 26-3. TAP Controller State Diagram
1
Test-Logic-Reset
0
II:26-10
Figure 26-3 for illustration of the state transitions that occur in the TAP
0
1
Run-Test/Idle
1
0
NOTE: All state transitions are based on the value of TMS.
1
Select-DR-Scan
0
Capture-DR
0
Shift-DR
0
1
1
Exit1-DR
0
Pause-DR
0
1
Exit2-DR
1
Update-DR
1
0
®
Intel PXA27x Processor Family Design Guide
1
Select-IR-Scan
0
1
Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR
0
1
0
Exit2-IR
1
Update-IR
1
0