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Figure 2-6. PBGA 23mm x 23mm Component Layout Placement Guide (Top View)
MEMORY
I/O
2.2.3
PCB Escape Routing
One important consideration when implementing chip scale packages (CSP) on a PCB, is the
design of escape routing. Escape routing is the layout of the package signals from underneath the
package to other components on the PCB. Escape routing requires high density interconnect (HDI)
PCB fabrication technology or micro-vias to route signals from the inner rows of balls on these
packages:
•
0.5 mm (0.0197 inches) ball pitch packages (for example, VF-BGA)
•
0.65 mm (0.0256 inches) ball pitch packages (for example, FS-CSP)
®
Intel
PXA27x Processor Family Design Guide
MEMORY I/O
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
A
A
B
1
2
3
4
5
6
7
MEMORY I/O
BASEBAND I/F
CORE
BATT
PLL
SRAM
IO
8
9
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16
8
9
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PERIPHERAL I/O
USB
LCD
IO
BB
PCB Design Guidelines
USB
17
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20
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22
A
B
C
D
E
F
USIM
G
H
J
K
L
LCD
M
N
P
R
T
U
V
CLOCK &
W
POWER
Y
CONTROL
A
A
A
B
17
18
19
20
21
22
VCC BALL
USIM
MEM
VSS BALL
I:2-7
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