Schematics/Block Diagram; Layout Notes; Passive Color Dual-Scan Mode; Signals - Intel PXA27 Series Design Manual

LCD Interface
7.5.4.2

Schematics/Block Diagram

See Figure 7-4
Figure 7-4. Passive Color Single-Scan Display Typical Connection
7.5.4.3

Layout Notes

Refer to Section 7.4, "Layout Notes,"
7.5.5

Passive Color Dual-Scan Mode

Passive color dual-scan panels drive 5 1/3 data values per clock cycle. These panels are connected
and programmed as if they are two separate panels, each with half the numbers of lines.
7.5.5.1

Signals

For passive color dual-scan displays, see
connections between the PXA27x processor and LCD panel.
II:7-12
for illustration of typical connections for a single-scan color passive display.
LDD<0>
LDD<1>
LDD<2>
LDD<3>
LDD<4>
LDD<5>
Top left Blue
LDD<6>
Top left Green
LDD<7>
Top left Red
L_PCLK_WR
L_LCLK_A0
L_FCLK_RD
L_BIAS
for layout notes and considerations.
Table 7-7 for description of the pins required for
®
Intel PXA27x Processor Family Design Guide
D0
D1
D2
D3
D4
D5
D6
D7
PIXEL_CLOCK
LINE_CLOCK
FRAME_CLOCK
BIAS