Intel PXA27 Series Design Manual page 4

Contents
Part II
1 Introduction to Part II .............................................................................................................II: 1-1
2 Package and Pins ...................................................................................................................II: 2-1
3 Clocks and Power Interface...................................................................................................II: 3-1
3.1 Overview........................................................................................................................II: 3-1
3.2 Signals ...........................................................................................................................II: 3-1
3.2.1 Clock Interface Signals .....................................................................................II: 3-1
3.2.2 Power Manager Interface Control Signals ........................................................II: 3-2
3.2.3 Power Enable (PWR_EN).................................................................................II: 3-3
3.2.3.1
3.2.3.2
3.2.3.3
3.2.3.4
3.2.3.5
3.3 Block Diagram ...............................................................................................................II: 3-4
3.4 Layout Notes..................................................................................................................II: 3-6
3.5 Modes of Operations .....................................................................................................II: 3-6
3.5.1 Clock Interface..................................................................................................II: 3-6
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.4
3.5.2 Power Interface.................................................................................................II: 3-8
3.5.2.1
4 Internal SRAM .........................................................................................................................II: 4-1
4.1 Overview........................................................................................................................II: 4-1
4.2 Signals ...........................................................................................................................II: 4-1
4.3 Block Diagram ...............................................................................................................II: 4-1
4.4 Layout Notes..................................................................................................................II: 4-2
5 DMA Controller Interface .......................................................................................................II: 5-1
5.1 Overview........................................................................................................................II: 5-1
5.2 Signals ...........................................................................................................................II: 5-1
5.3 Block Diagram ...............................................................................................................II: 5-2
5.4 Layout Notes..................................................................................................................II: 5-2
5.5 Modes of Operation .......................................................................................................II: 5-3
5.5.1 Fly-By DMA Transfers ......................................................................................II: 5-3
5.5.1.1
5.5.1.2
5.5.1.3
5.5.2 Flow-Through DMA Transfers ..........................................................................II: 5-5
5.5.2.1
5.5.2.2
5.5.2.3
6 System Memory Interface ......................................................................................................II: 6-1
6.1 Overview........................................................................................................................II: 6-1
6.2 Signals ...........................................................................................................................II: 6-3
iv
System Power Enable (SYS_EN) .....................................................II: 3-3
Power Manager I2C Clock (PWR_SCL) ...........................................II: 3-3
Power Manager I2C Data (PWR_SDA) ............................................II: 3-3
nVDD_FAULT ...................................................................................II: 3-3
nBATT_FAULT .................................................................................II: 3-4
Using the On-Chip Oscillator with a 32.768-KHz Crystal..................II: 3-7
Using an External 32.768-KHz Clock................................................II: 3-7
Using the On-Chip Oscillator with a 13.000-MHz Crystal .................II: 3-7
Using an External 13.00-MHz Clock .................................................II: 3-8
Power Supplies .................................................................................II: 3-8
Signals ..............................................................................................II: 5-3
Block Diagram...................................................................................II: 5-4
Layout Notes.....................................................................................II: 5-4
Signals ..............................................................................................II: 5-5
Block Diagram...................................................................................II: 5-5
Layout Notes.....................................................................................II: 5-6
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Intel PXA27x Processor Family Design Guide