Intel PXA27 Series Design Manual page 149

•
As shown in
used for USB device controller data, but SW2 is enabled and disabled by hardware when the
UDC is idle and receiving data from an upstream device as specified in the Pull-up/Pull-down
Resistors Engineering Change Notice to the USB 2.0 Specification.
See Table 12-2
Figure 12-5. Host Port 2 OTG Transceiver
UP2OCR[DPPUE/DMPUE]
UDC txen
UHC port 2 txen
UP2OCR[HXOE]
UDC TxD+/TxD-
UHC Port 2 TxD+/TxD-
UP2OCR[HXS]
RxD+/RxD-
UP2OCR[DPPDE/DMPDE]
Table 12-2.
Controller
Selected
USB Host
USB Device
† SW1, SW2 and SW3 refer to the switches shown in
Note: There are programming requirements for disabling and enabling the transceiver and pull-up/pull-
down resistors for USB host port 2 and for sleep and standby mode operation. Refer to the Intel
PXA27x Processor Family Developers Manual for additional information.
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Intel PXA27x Processor Family Design Guide
Figure 12-5, SW2 on the D+ and D- pads is disabled when host port 2 is being
for the list of switch settings used for the USB Host and USB Device controller I/O.
ENB
Host Port 2 OTG Transceiver Switch Control Settings
D+ Transceiver
SW1† SW2†
Disabled Disabled
Hardware
Enabled
controlled
USB Host Port 2 Transceiver Pad
R
PU2
SW2
900 - 1.575 K Ohms
SW1
R
PU1
525 - 1.515 K Ohms
D+/D-
SW3
R
PD
14.25 - 24.8 K Ohms
SW3† SW1†
Enabled Disabled
Disabled Disabled
.
Figure 12-5
'USB Client Controller
D- Transceiver
SW2† SW3†
Disabled Enabled
Disabled Disabled
II:12-7
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