Jtag Debug; Overview - Intel PXA27 Series Design Manual

JTAG Debug

This chapter describes the boundary-scan (JTAG) features of Intel
(PXA27x processor). The boundary-scan interface provides a means of driving and sampling the
external pins of the processor, regardless of the state of the core. This function tests the processor's
electrical connections to the circuit board and (in conjunction with other devices on the circuit
board having a similar interface) the integrity of the circuit board connections between devices.
26.1

Overview

The boundary-scan interface intercepts each external connection in the processor using a
boundary-scan cell. The boundary-scan cells combine to form a serial shift register, the boundary-
scan register.
The interface is controlled through five dedicated test access port (TAP) pins as described in
26-1:
•
TDI
•
TMS
•
TCK
•
nTRST
•
TDO
The boundary-scan test-logic elements include:
•
TAP pins
•
TAP controller
•
Instruction register
•
Boundary-scan register
•
Bypass register
•
Device identification register
•
Data-specific register(s)
See Figure 26-1
®
Intel PXA27x Processor Family Design Guide
for illustration of all the above elements.
26
®
PXA27x Processor Family
Table
II:26-1