Intel PXA27 Series Design Manual page 10

Contents
26 JTAG Debug..........................................................................................................................II: 26-1
26.1 Overview......................................................................................................................II: 26-1
26.2 Features.......................................................................................................................II: 26-2
26.3 Signal Descriptions ......................................................................................................II: 26-3
26.4 Operation .....................................................................................................................II: 26-3
26.4.1 TAP Controller Reset......................................................................................II: 26-3
26.4.2 Pull-Up Resistors ............................................................................................II: 26-4
26.4.3 JTAG Instruction Register and Instruction Set................................................II: 26-5
26.4.4 Test Data Registers ........................................................................................II: 26-7
26.4.4.1 Bypass Register..............................................................................II: 26-7
26.4.4.2 Boundary-Scan Register.................................................................II: 26-8
26.4.4.3 Data-Specific Registers ..................................................................II: 26-9
26.4.4.4 Flash Data Register ........................................................................II: 26-9
26.4.4.5 Intel XScale
26.4.5 Test Access Port (TAP) Controller................................................................II: 26-10
26.4.5.1 Test-Logic-Reset State .................................................................II: 26-11
26.4.5.2 Run-Test/Idle State .......................................................................II: 26-11
26.4.5.3 Select-DR-Scan State...................................................................II: 26-11
26.4.5.4 Capture-DR State .........................................................................II: 26-11
26.4.5.5 Shift-DR State ...............................................................................II: 26-11
26.4.5.6 Exit1-DR State ..............................................................................II: 26-12
26.4.5.7 Pause-DR State ............................................................................II: 26-12
26.4.5.8 Exit2-DR State ..............................................................................II: 26-12
26.4.5.9 Update-DR State...........................................................................II: 26-12
26.4.5.10 Select-IR-Scan State ....................................................................II: 26-13
26.4.5.11 Capture-IR State ...........................................................................II: 26-13
26.4.5.12 Shift-IR State.................................................................................II: 26-13
26.4.5.13 Exit1-IR State................................................................................II: 26-13
26.4.5.14 Pause-IR State..............................................................................II: 26-13
26.4.5.15 Exit2-IR State................................................................................II: 26-14
26.4.5.16 Update-IR State ............................................................................II: 26-14
26.5 Register Descriptions.................................................................................................II: 26-15
26.5.1 JTAG Device Identification (ID) Register ......................................................II: 26-15
26.5.2 JTAG Test Data Registers............................................................................II: 26-16
26.5.3 Debug Registers ...........................................................................................II: 26-16
26.6 Test Register Summary .............................................................................................II: 26-16
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27 Intel Quick Capture Technology .......................................................................................II: 27-1
27.1 Overview......................................................................................................................II: 27-1
27.2 Feature List..................................................................................................................II: 27-2
27.3 Signals .........................................................................................................................II: 27-2
27.4 Block Diagram .............................................................................................................II: 27-3
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Data Registers..........................................................II: 26-9
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Intel PXA27x Processor Family Design Guide