Intel PXA27 Series Design Manual page 13

Contents
8-1 Standard SSP Configuration Scheme Block Diagram ...........................................................II: 8-4
8-2 External Clock Source Configuration Scheme Block Diagram ..............................................II: 8-4
8-3 External Clock Enable Configuration Scheme Block Diagram ..............................................II: 8-5
8-4 Internal Clock Enable Configuration Scheme Block Diagram................................................II: 8-6
9-1 Linear Technology DAC with I2C Interface............................................................................II: 9-2
9-2 Using an Analog Switch to Allow a Second CF Card ............................................................II: 9-3
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9-3 I C Pull-Ups and Pull-Downs.................................................................................................II: 9-4
10-1 FFUART Interface Block Diagram .......................................................................................II: 10-4
10-2 BTUART Interface Block Diagram .......................................................................................II: 10-5
10-3 STUART Interface Block Diagram .......................................................................................II: 10-6
11-1 Fast Infrared Controller Port Interface Block Diagram.........................................................II: 11-2
12-1 USB Client Interface Block Diagram....................................................................................II: 12-2
12-2 Self Powered Device when GPIOn and GPIOx are Different Pins ......................................II: 12-3
12-3 Self-Powered Device when GPIOn and GPIOx are Same Pins ..........................................II: 12-4
12-4 USB OTG Configurations ....................................................................................................II: 12-6
12-5 Host Port 2 OTG Transceiver ..............................................................................................II: 12-7
12-6 Connection to External OTG Transceiver............................................................................II: 12-8
12-7 Connection to External OTG Charge Pump ......................................................................II: 12-10
12-8 Connection to OTG ID .......................................................................................................II: 12-11
12-9 PXA27x Processor Connection to External USB Transceiver ...........................................II: 12-12
13-1 AC '97 Controller to CODEC Block Diagram .......................................................................II: 13-2
14-1 I2S Controller Interface Block Diagram ...............................................................................II: 14-3
14-2 PXA27x Processor Provides BITCLK ..................................................................................II: 14-5
14-3 PXA27x Processor Receives BITCLK .................................................................................II: 14-6
15-1 MMC Protocol Interface Block Diagram...............................................................................II: 15-5
15-2 MMC Protocol Interface Schematic Diagram.......................................................................II: 15-6
15-3 SD and SDIO Protocol Interface Block Diagram .................................................................II: 15-8
15-4 SD and SDIO Protocol Interface Schematic Diagram .........................................................II: 15-9
15-5 SPI Protocol Interface Block Diagram ...............................................................................II: 15-12
17-1 Memory Stick Implementation Block Diagram .....................................................................II: 17-2
18-1 Keypad Interface Block Diagram .........................................................................................II: 18-3
18-2 Keypad Matrix and Direct Keys Block Diagram (with No Rotary Encoder)..........................II: 18-7
18-3 Keypad Matrix and Direct Keys Block Diagram (with One Rotary Encoder) .......................II: 18-9
18-4 Keypad Matrix and Direct Keys Block Diagram (with Two Rotary Encoders)....................II: 18-11
19-1 Connectivity USIM Card and PXA27x Processor USIM Interface using UVSx signals .......II: 19-4
19-2 Connectivity USIM Card and PXA27x Processor USIM Interface Using nUEN ..................II: 19-5
20-1 USB Host (Port 1 or Port 2) Differential Connections Block Diagram..................................II: 20-2
20-2 PXA27x Processor Host 2 Single-Ended Connection to External Transceiver ...................II: 20-3
20-3 PXA27x Processor Host 3 Connection to External USB Transceiver..................................II: 20-4
21-1 Example HZ_CLK Block Diagram........................................................................................II: 21-2
22-1 OS Timer Block Diagram .....................................................................................................II: 22-2
23-1 PWM Block Diagram For Applications Requiring a Filter ....................................................II: 23-2
25-1 Interrupt Controller Block Diagram ......................................................................................II: 25-3
26-1 Test Access Port (TAP) Block Diagram...............................................................................II: 26-2
26-2 PXA27x Scan Chain Arrangement ......................................................................................II: 26-5
26-3 TAP Controller State Diagram ...........................................................................................II: 26-10
27-1 Block Diagram for 8-bit Master Parallel Interface ................................................................II: 27-3
27-2 Interface Options Summary .................................................................................................II: 27-4
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Intel PXA27x Processor Family Design Guide xiii