Intel PXA27 Series Design Manual page 5

6.3 Block Diagram ...............................................................................................................II: 6-5
6.4 Memory Controller Layout Notes ...................................................................................II: 6-6
6.4.1 Memory Controller Routing Guidelines for 0.5mm and 0.65 mm Ball Pitch......II: 6-6
6.4.1.1
(Excluding SDCLK<x> and SDCAS).................................................................II: 6-6
6.4.1.2
6.4.1.3
6.5 Modes of Operation Overview .......................................................................................II: 6-9
6.5.1 SDRAM Interface ..............................................................................................II: 6-9
6.5.1.1
6.5.1.2
6.5.1.3
6.5.2 Flash Memory Interface (Asynchronous/Synchronous) ..................................II: 6-15
6.5.2.1
6.5.2.2
6.5.2.3
6.5.3 ROM Interface ................................................................................................II: 6-17
6.5.3.1
6.5.3.2
6.5.3.3
6.5.4 SRAM Interface ..............................................................................................II: 6-18
6.5.4.1
6.5.4.2
6.5.4.3
6.5.5 Variable Latency Input/Output (VLIO) Interface..............................................II: 6-21
6.5.5.1
6.5.5.2
6.5.5.3
6.5.6 PC Card (PCMCIA) Interface..........................................................................II: 6-23
6.5.6.1
6.5.6.2
6.5.6.3
6.5.7 Alternate Bus Master Interface .......................................................................II: 6-29
6.5.7.1
6.5.7.2
6.5.7.3
7 LCD Interface ..........................................................................................................................II: 7-1
7.1 Overview ........................................................................................................................II: 7-1
7.2 Signals ...........................................................................................................................II: 7-2
7.3 Schematics/Block Diagram ............................................................................................II: 7-3
7.4 Layout Notes..................................................................................................................II: 7-3
7.4.1 Contrast Voltage ...............................................................................................II: 7-3
7.4.2 Backlight Inverter ..............................................................................................II: 7-4
7.4.3 Signal Routing and Buffering ............................................................................II: 7-4
7.4.4 Panel Connector ...............................................................................................II: 7-5
7.5 Modes of Operation Overview .......................................................................................II: 7-6
7.5.1 Passive Monochrome Single-Scan Mode .........................................................II: 7-6
7.5.1.1
7.5.1.2
7.5.1.3
7.5.2 Passive Monochrome Single-Scan Double-Pixel Mode....................................II: 7-8
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Intel PXA27x Processor Family Design Guide
System Bus Recommended Signal Routing Guidelines
SDCLK and SDCAS Recommended Signal Routing Guidelines ......II: 6-7
Minimum Board Stack-up Configuration used for Signal Integrity ....II: 6-8
SDRAM Signals ................................................................................II: 6-9
SDRAM Memory Block Diagram.....................................................II: 6-11
SDRAM Layout Notes.....................................................................II: 6-12
Flash Memory Signals ....................................................................II: 6-15
Flash Block Diagram.......................................................................II: 6-16
Flash Layout Note...........................................................................II: 6-16
ROM Signals...................................................................................II: 6-17
ROM Block Diagram .......................................................................II: 6-18
ROM Layout Notes .........................................................................II: 6-18
SRAM Signals.................................................................................II: 6-19
SRAM Block Diagram .....................................................................II: 6-20
SRAM Layout Notes .......................................................................II: 6-20
VLIO Memory Signals .....................................................................II: 6-22
VLIO Block Diagram .......................................................................II: 6-23
VLIO Memory Layout Notes............................................................II: 6-23
PC Card Signals .............................................................................II: 6-25
PC-Card Block Diagrams................................................................II: 6-26
PC Card Layout Notes ....................................................................II: 6-29
Alternate Bus Master Signals..........................................................II: 6-31
Alternate Bus Master Block Diagram ..............................................II: 6-32
Alternate Bus Master Layout Notes ................................................II: 6-32
Signals ..............................................................................................II: 7-6
Schematics/Block Diagram ...............................................................II: 7-7
Layout Notes.....................................................................................II: 7-7
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