Intel PXA27 Series Design Manual page 285

Glossary
Little Endian. Method of storing data that places the least significant byte of multiple-byte values at lower storage
addresses. For example, a 16-bit integer stored in little endian format places the least significant byte at the lower
address and the most significant byte at the next address.
LOA. Loss of bus activity characterized by an SOP without a corresponding EOP.
Low-speed. USB operation at 1.5 Mbps. See also Full-speed and High-speed.
LSb. Least significant bit
LSB. Least significant Byte
LVDS. Low-voltage Differential Signal
MAC. Multiply Accumulate Unit
Mbps. Transmission rate expressed in megabits per second.
MBps. Transmission rate expressed in megabytes per second.
MC. Media Center. A combination digital set-top box, video and music jukebox, personal video recorder and an
Internet gateway and firewall that hooks up to a broadband connection.
MCI. Memory Controller Interface
Message Pipe. A bidirectional pipe that transfers data using a request/data/status paradigm. The data has an
imposed structure that allows requests to be reliably identified and communicated.
Microframe. A 125 microsecond time base established on high-speed buses.
MMC. Multimedia Card. Small form factor memory and I/O card
MMX Technology. The Intel® MMX™ technology comprises a set of instructions that are designed to greatly
enhance the performance of advanced media and communications applications. Refer to Chapter 10 of the Intel
Architecture Software Developers Manual, Volume 3: System Programming Guide, Order #245472.
Mobile Station. Cellular Telephone handset
M-PSK. Multilevel Phase Shift Keying. A convention for encoding digital data in which there are multiple states.
MMU. Memory Management Unit. Part of the Intel XScale®core.
MSb. Most significant bit
MSB. Most significant byte
MSL. Mobile Scalable Link
NAK. Handshake packet indicating a negative acknowledgment.
Non Return to Zero Invert (NRZI). A method of encoding serial data in which ones and zeroes are represented by
opposite and alternating high and low voltages where there is no return to zero (reference) voltage between encoded
bits. Eliminates the need for clock pulses.
NRZI. See Non Return to Zero Invert.
Object. Host software or data structure representing a USB entity.
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Intel PXA27x Processor Family Design Guide Glossary-9