Intel PXA27 Series Design Manual page 260

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Intel PXA27x Processor and Intel
— TCR register has an additional field to enhance TMED support.
— FDADR1-FDADR6 registers added to support new overlays and cursor.
— FBR1-FBR6 registers added to support new overlays and cursor.
— FSADR1-FSADR6 registers added to support new overlays and cursor.
— FIDR1-FIDR6 registers added to support new overlays and cursor.
— LDCMD1-LDCMD6 registers added to support new overlays and cursor.
— LCDBSCNTR register has been added to support programmable output buffer strength.
— PRSR register has been added to support reading data from frame buffer panels.
— LCSR0 register has been expanded to support more channels and read status for frame
buffer panels.
— LCSR1 register has been added to support the new overlays.
— The registers that remains unchanged are: LCCR1, LCCR2, TRGBR, FDADDR0, FBR0,
FSADR0, FIDR0, LDCMD0 and LIIDR.
D.8 SSP Serial Port
The PXA27x processor provides three SSPs whereas the PXA25x processor provides a single SSP.
The PXA27x processor SSP controller retains compatibility with the original protocols
implemented in the PXA25x processor and adds support for a new Programmable Serial Protocol
(PSP). The PSP supports register programmable frame sync in addition to programmable start and
stop delays.
The PXA27x processor SSP controller also provides greater flexibility than the PXA25x processor
SSP controller through these enhancements:
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Transfer rates up to 13 Mbps
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4-bit to 32-bit serial data transfers
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Master or slave operation for both clock and frame sync signals
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Flexible clock source selection from the 13-MHz master clock, the network clock input, or the
dedicated SSP external clock input
D-6
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PXA25x Processor Differences
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Intel PXA27x Processor Family Design Guide