Intel PXA27 Series Design Manual page 228

JTAG Debug
Table 26-2. IEEE 1149.1 Boundary-Scan Instruction Set
Instruction Instruction
Code Type
0b000_0000 mandatory public
0b000_0001 mandatory public
0b000_0010 user defined
0b000_0011 private
0b000_0100 optional public
0b000_0101 private
-
0b000_0110
0b000_0111 user defined
0b000_1000 optional public
0b000_1001 user defined
Table 26-3. IEEE 1149.1 Boundary-Scan Instruction Descriptions (Sheet 1 of 2)
Instruction Opcode
extest
0b000_0000
IEEE 1149.1
required
sample/
preload
0b000_0001
IEEE 1149.1
required
dbgrx 0b000_0010 Refer to
clamp 0b000_0100
ldic 0b000_0111
highz 0b000_1000
dcsr 0b000_1001 Refer to
dbgtx 0b001_0000 Refer to
II:26-6
Instruction
Name
extest
sample/preload
dbgrx
private
clamp
private
ldic
highz
dcsr
The extest instruction initiates testing of external circuitry, typically board-level interconnections and
off-chip circuitry. The extest instruction connects the boundary-scan register between TDI and TDO
in the Shift-DR state only. When extest is selected, output signal pin values are driven by values
shifted into the boundary-scan register and change only on the falling-edge of TCK in the Update-
DR state. When extest is selected, all system input-pin states are loaded into the boundary-scan
register on the rising edge of TCK in the Capture-DR state. Values shifted into input latches in the
boundary-scan register are never used by the processor's internal logic.
The sample/preload instruction performs two functions:
• When the TAP controller is in the Capture-DR state, the sample instruction executes on the
rising edge of TCK and provides a snapshot of the component's normal operation without
interfering with that operation. The instruction causes boundary-scan register cells to sample
data entering and leaving the processor.
• When the TAP controller is in the Update-DR state, the preload instruction occurs on the falling
edge of TCK. This instruction causes the data held in the boundary-scan cells to be transferred
to the slave register cells. Typically, the slave-latched data is then applied to the system outputs
by means of the extest instruction.
Chapter 26, "Software Debug,"
The clamp instruction allows the states of the signals driven from the PXA27x processor pins to be
determined from the boundary-scan register while the bypass register is selected as the serial path
between TDI and TDO. Signals driven from the component pins do not change while the clamp
instruction is selected.
Refer to Section 26.4.6.3, "Downloading Code into the Instruction Cache,"
Processor Family Developers Manual .
The highz instruction floats all three-statable output and I/O pins. When this instruction is active, the
bypass register is connected between TDI and TDO. This register is accessed using the JTAG TAP
throughout the device operation. The bypass register is also accessed with the bypass instruction
Chapter 26, "Software Debug,"
Chapter 26, "Software Debug,"
Instruction Code
0b000_1010 - 0b000_1111
0b001_0000
0b001_0001- 0b011_0101
0b011_0110
0b011_0111
0b011_1000 - 0b111_1101
0b111_1110
0b111_1111
Description
®
in the Intel PXA27x Processor Family Developers Manual .
®
in the Intel PXA27x Processor Family Developers Manual .
®
in the Intel PXA27x Processor Family Developers Manual .
®
Intel PXA27x Processor Family Design Guide
Instruction Instruction
Type Name
private private
user defined dbgtx
private private
user defined flashload
user defined flashprogram
private private
optional public idcode
mandatory public bypass
®
in the Intel PXA27x
.