Intel PXA27 Series Design Manual page 98

System Memory Interface
8. The PXA27x processor asserts SDCKE at time (t + 4 x Tmem).
During the three-state period, both MBREQ and MBGNT remain high and an external device must
assume control of the three-stated pins. The external device must drive all the three-stated pins
even if some are not actually used. Otherwise, floating inputs causes excessive crossover current or
erroneous SDRAM commands.
Note that during the three-state period, the PXA27x processor cannot perform SDRAM refresh
cycles. The SDRAM memory controller of the PXA27x processor issues a CBR (auto refresh)
command prior to releasing control of the bus. If the system is populated with SRAM in partition 0,
the alternate master must assume the responsibility for SDRAM integrity during this period.
Otherwise, design the system such that the period of alternate mastership is limited to much less
than the refresh period, or that the alternate master implement a refresh counter enabling it to
perform refreshes at the proper intervals. In other words, the alternate bus master must release
control from the bus before the next CBR command is due. This is 7.8 µs for SDRAM with 13 row
address lines, 15.6 µs for SDRAM with 12 row address lines, 31.0 µs for SDRAM with 12 row
address lines.
To give up ownership of the bus, perform the procedure according to the release sequence and
timing:
1. Alternate master de-asserts MBREQ.
2. The PXA27x processor de-asserts SDCKE at time (t).
3. The PXA27x processor de-asserts MBGNT at time (t + 1 x Tmem).
4. Alternate master three-states SDRAM outputs prior to time (t + 2 x Tmem).
5. The PXA27x processor drives SDRAM outputs at time (t + 3 x Tmem).
6. The PXA27x processor asserts SDCKE at time (t + 4 x Tmem).
7. The PXA27x processor memory controller performs an SDRAM refresh if SDRAM clocks
and clock enable are turned on.
8. The PXA27x processor memory controller sends an MRS command to the SDRAMs if the
MDCNFG[SA1110_x] bit is turned on. This is done to change the SDRAM burst length back
to 4 instead of 1.
Alternate bus master mode is set up by writing these registers:
•
Write the GPIO Pin Direction register (GPDR_x) to set the bit corresponding to MBGNT as an
output and clear the bit corresponding to MBREQ an input.
•
Write the GPIO Alternate Function register (GAFR0_x) to set the bits that map the alternate
functions on the specified GPIO pins to the Alternate Bus Master mode operation.
II:6-30
®
Intel PXA27x Processor Design Guide