Intel PXA27 Series Design Manual page 78

System Memory Interface
Table 6-5. SDRAM I/O Signals (Sheet 2 of 2)
Signal Name
nSDRAS
nSDCAS
nWE
RDnWR
II:6-10
Direction Polarity
Output Active Low
Output Active Low
Output Active Low
Miscellaneous I/O Signals
Output Active High
Description
Row address for SDRAM
Column strobe for SDRAM
Write enable for SDRAM and static memory
Data direction signal to be used by output transceivers
0 = MD<31:0> is driven by the PXA27x processor
1 = MD<31:0> is not driven by the PXA27x processor
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Intel PXA27x Processor Design Guide