Interfacing To A Matrix Keypad - Intel PXA27 Series Design Manual

For a given configuration of the PXA27x processor GPIO, some direct key inputs are not
connected to the keypad interface if their corresponding GPIO pins are being used as inputs/
outputs for other functional blocks. For example:
•
GPIO pins corresponding to direct key inputs 2 and 3 are used as inputs/outputs for other
blocks and hence unavailable for the keypad interface. In such a case, the KP_DKIN<3:2>
input signals is guaranteed a logic 0 on them all the time, denoting no activity on direct keys 2
and 3.
•
The rest of the direct key are utilized as inputs KP_DKIN<1:0> and KP_DKIN<7:4> and
connected with rotary encoders or direct keys. By specifying the number of direct keys in the
Keypad Control register as 8 (KPC[DKN] = "111"), a logic 0 on direct key inputs 2 and 3 is
guaranteed and no activity is detected on them.
For details about GPIO configuration, refer to the GPIO section of the Intel
Family Developers Manual.
18.4.6

Interfacing to a Matrix Keypad

When interfacing to a matrix keypad, the KP_MKINx and KP_MKOUTx signals must be
connected sequentially from KP_MKIN0 to KP_MKIN7 and from KP_MKOUT0 to
KP_MKOUT7. The number of columns in the keypad signifies the highest order KP_MKOUTx
signal minus one to be used. The number of rows in the keypad signifies the highest order
KP_MKINx signal minus one to be used.
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Intel PXA27x Processor Family Design Guide
Keypad Interface
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PXA27x Processor
II:18-5