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JTAG Debug
26.4.5.6
Exit1-DR State
Exit1-DR is a temporary controller state. When the TAP controller is in the Exit1-DR state and
TMS is held high on the rising edge of TCK, the controller enters the Update-DR state, which
terminates the scanning process. If TMS is held low on the rising edge of TCK, the controller
enters the Pause-DR state.
The current instruction does not change while the TAP controller is in this state. The test data
register selected by the current instruction retains its previous value during this state.
26.4.5.7
Pause-DR State
The Pause-DR state allows the test controller to temporarily halt the shifting of data through the
test data register in the serial path between TDI and TDO. The test data register selected by the
current instruction retains its previous value during this state. The current instruction does not
change in this state.
The controller remains in this state as long as TMS is low. When TMS goes high on the rising edge
of TCK, the controller moves to the Exit2-DR state.
26.4.5.8
Exit2-DR State
Exit2-DR State is a temporary state. If TMS is held high on the rising edge of TCK, the controller
enters the Update-DR state, which terminates the scanning process. If TMS is held low on the
rising edge of TCK, the controller enters the Shift-DR state.
The current instruction does not change while the TAP controller is in this state. The test data
register selected by the current instruction retains its previous value during this state.
26.4.5.9
Update-DR State
The boundary-scan register is provided with a latched parallel output. This output prevents changes
at the parallel output while data is shifted in response to the extest or sample/preload instructions.
When the boundary-scan register is selected while the TAP controller is in the Update-DR state,
data is latched onto the boundary-scan register's parallel output from the shift register path on the
falling edge of TCK. The data held at the latched parallel output does not change unless the
controller is in this state.
While the TAP controller is in this state, the test data register selected by the current instruction
retains its previous value. The current instruction does not change while the TAP controller is in
this state.
When the TAP controller is in this state and TMS is held high on the rising edge of TCK, the
controller enters the Select-DR-Scan state. If TMS is held low on the rising edge of TCK, the
controller enters the Run-Test/Idle state.
II:26-12
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Intel
PXA27x Processor Family Design Guide
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