Rom Block Diagram; Rom Layout Notes; Sram Interface; Block Diagram Connecting Rom To Ncs<0 - Intel PXA27 Series Design Manual

System Memory Interface
6.5.3.2

ROM Block Diagram

See Figure 6-7
memory controller on chip select 0. Refer to this diagram when connecting SRAM and VLIO
memories using a 16-bit interface and when using the procedure for connecting byte enable signals
and data signals.
Figure 6-7. Block Diagram Connecting ROM to nCS<0>
PXA27x Memory
Controller
6.5.3.3

ROM Layout Notes

Refer to Section 6.4
®
Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel
Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information.
6.5.4

SRAM Interface

For SRAM, DQM<3:0> signals are used for the write byte enables, where DQM<3> corresponds
to the MSB in little endian mode. The processor supplies 26-bits of byte address for access of up to
128 Mbytes per chip select.
II:6-18
for illustration of the connection between a 16-bit ROM and the PXA27x processor
nCS<5:0>
nOE
MA<25:1>
DQM<3:0>
MD<31:0>
for recommendations on trace lengths, size, and routing guidelines. Refer to
2Mx16
ROM
0
nCS
nOE
21:1
A<20:0>
0 DQML
1
DQMH
15:0
DQ<15:0>
MEM_005_P2
®
Intel PXA27x Processor Design Guide
®
PXA27x