Intel PXA27 Series Design Manual page 258

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Intel PXA27x Processor and Intel
D.6 Memory Controller
The memory controllers in the PXA27x processor and PXA25x processor are similar with the
following exceptions.
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Features added to the PXA27x processor memory controller:
— Support for low power SDRAM includes:
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— Support 128 Mbytes/256 Mbytes partitions
— Programmable Buffer Strength on memory I/O signals
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Enhancement to the memory controller of the PXA27x processor:
— SDCLK<0> divide down option by 4 with respect to CLK_MEM
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Features removed from the memory controller of the PXA27x processor:
— Support for Synchronous Mask ROM (SMROM)
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Signals removed from the memory controller of the PXA27x processor:
— SDCKE<0>
— BOOT_SEL<2:1>
Changes to the registers within the memory controller of the PXA25x processor were required to
support the new features and removal of support for the SMROM in the memory controller of the
PXA27x processor:
— The MDCNFX register has been added to support larger SDRAM partitions.
— The SCNTR0 - BSNTR3 registers have been added to support programmable buffer
strength.
— The MDMRSLP register has been added to support low power SDRAM MRS command.
— The MDREFR register has additional bit added to support SDCLK0 divide by 4 option.
— The SXCNFG and BOOT_DEF registers have additional bits removed as a result of not
supporting SMROM in the PXA27x processor memory controller.
— The registers that remain unchanged are:
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D-4
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PXA25x Processor Differences
Support for 1.8 volt memory I/O
Additional MRS register for low power SDRAM support
MDCNFG
MDMRS
MSC0 - MSC2
MCMEM0
MCMEM1
MCATT0
MCATT1
MCIO0
MCIO1
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Intel PXA27x Processor Family Design Guide