Intel PXA27 Series Design Manual page 257

D.5 DMA Controller
The DMA controllers in the PXA27x processor and PXA25x processor are similar with these
exceptions:
•
Features added to the DMA controller of the PXA27x processor:
— Additional 16 DMA channels for a total of 32 DMA channels
— Support fly-by transfers
•
Enhancements to the DMA controller of the PXA27x processor:
— Descriptor Compare and Branching Mode
— Byte boundary alignment for source and target addresses (down from 64-bit aligned)
— End of Receive status/control bits for transfers from the internal peripherals
•
Support for big endian transfers to and from any DMA devices has been removed.
•
Signals added to the PXA27x processor DMA controller:
— DVAL<1:0> - Data Valid for fly-by transfers
•
Changes to the registers within the PXA25x processor DMA controller were required to
support the new features in the PXA27x processor DMA controller:
— FLYCNFG registers have been added to support fly-by transfers to external SDRAM.
— These registers have been added to support the additional internal peripheral device
requests:
◆
— These registers have been added to support the additional 16 DMA channels:
◆
◆
◆
◆
— The DDADRx, DCMDx, and DCSRx registers have additional bits added to support the
descriptor branch and compare mode and the end of receive control and status
functionality.
— The DINT register had additional bit added to support the additional 16 DMA channels.
— The DRCMRx register has the CHLNUM bitfield increased by 1.
Note: The registers that remains unchanged are the DSADRx and DTADRx registers.
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Intel PXA27x Processor Family Design Guide
®
Intel PXA27x Processor and Intel
DRCMR38 - DRCMR67
DCMD16 - DCMD31
DDADR16 - DDADR31
DSADR16 - DSADR31
DTADR16 - DTADR31
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PXA25x Processor Differences
D-3