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PXA27x DVK Block Diagram
Figure A-7. JTAG Block Diagram
App
Processor
Comm
Processor
JTAG DSP
Test pads
JTAG Stake
Pins
A-8
2 Switches:
00: PXA27x
01: Garson
10: PXA27x & Garson
Switch
11: PXA27x, Garson, CPLD2, EEPROM & FPGA
Switch
Can also re-progam CPLD logic for special software needs
CPLD1
Auxiliary
Comms
JTAG
Stake pins
CPLD2
EEPROM
PCMCIA glue
Xcvr control
1.8V / 3.3V IO
5V tolerant
With Isolation switch enabled only
CPLD1 is seen on the JTAG chain
FPGA
Platform Registers
nCS2L
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Intel
PXA27x Processor Family Design Guide
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