Baseband Interface; Overview - Intel PXA27 Series Design Manual

Baseband Interface

16.1

Overview

This chapter describes the interface between Intel
processor) and a cellular baseband processor. PXA27x processor provides a high performance,
scalable baseband interface to Intel baseband processors described in a later revision of this
document.
However, PXA27x processor also provides other standard peripheral interfaces that support
connection to a number of wireless baseband subsystems from other manufacturers. For example,
in applications where the RF subsystem looks like a "wireless modem" to PXA27x processor, an
asynchronous UART connection supports full duplex communication up to 921.6 kbps. In
applications which require a faster synchronous interface, one or two SSP ports synchronized to an
external network clock provide another more flexible alternative for data rates up to 13 Mbps. The
PXA27x processor also provides the capability to run timer channels synchronous with the
network clock.
The PXA27x processor is configured to utilize both MSL and PCMCIA simultaneously. However,
this configuration impacts the usage of the LCD and MSL as described here:
•
Two of the LCD pins are required which prevents the use of 18-bit LCD.
GPIO [87:86] have alternate functions for:
— PCMCIA_nPCE1 and PCMCIA_nPCE2
— L_DD[16] and L_DD[17]
Therefore, enabling the PCMCIA signals renders the GPIO [87:86] unusable for LCD
connection.
•
The MSL is only used in a 1-bit configuration.
GPIOs 48, 50 and 51 have alternate functions for the three upper most MSL data bits:
— BB_OB_DAT[3:1] and BB_IB_DAT[3:1]
— PCMCIA_nPCE, PCMCIA_nPIOR, and PCMCIA_nPIOW
Therefore, enabling the GPIOs 48, 50, and 51 for PCMCIA support leaves only a single MSL
data bit to use.
•
The configuration allows the system to have:
— A PCMCIA interface
— A 1-bit MSL link
— A 16-bit LCD connection
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Intel PXA27x Processor Family Design Guide
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PXA27x Processor Family (PXA27x
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