Block Diagram; Layout Notes - Intel PXA27 Series Design Manual

Real Time Clock Interface
21.3

Block Diagram

Refer to Part II: Chapter 24, "General Purpose Input/Output Interface,"
information regarding the proper hardware implementation of the real time clock signal.
See Figure 21-1
between the PXA27x processor and peripheral using the HZ_CLK signal.
Figure 21-1. Example HZ_CLK Block Diagram
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21.4

Layout Notes

Refer to Part II: Chapter 24, "General Purpose Input/Output Interface,"
information regarding the proper layout practices for the real time clock signal.
The switching frequency of HZ_CLK is 1.0 Hz. Therefore, layout and routing considerations are
far less stringent as for other GPIOs and are somewhat relaxed. However, for best results, adhere to
all GPIO layout recommendations.
21-2
for illustration of a typical application of the HZ_CLK. The connection is directly
PXA27x
Processor
HZ_CLK
§§
®
Intel PXA27x Processor Family Design Guide
of this document for
Peripheral
Using
1 Hz
Signal
of this document for