Block Diagram - Intel PXA27 Series Design Manual

AC '97
13.3

Block Diagram

See Figure 13-1
the 12.288-MHz clock to the AC '97. This clock is then driven into the AC '97 controller unit on
the PXA27x processor and the AC '97 secondary CODEC.
Figure 13-1. AC '97 Controller to CODEC Block Diagram
II:13-2
for the block diagram showing AC '97 connections. The primary CODEC supplies
PXA27x
Processor
AC '97 Controller
AC97_RESET_n
AC97_SDATA_OUT
AC97_SYNC (48 kHz)
AC97_SDATA_IN_0
AC97_SDATA_IN_1
AC97_BITCLK (12.288 MHz) AC97_BITCLK (12.288 MHz)
AC97_SYSCLK (Optional)
(24.5 MHz)
®
Intel PXA27x Processor Family Design Guide
AC '97
nRESET
Primary
Codec
SDATA_OUT
SYNC
SDATA_IN
BIT_CLOCK
AC '97
nRESET
Secondary
Codec
SDATA_OUT
SYNC
SDATA_IN
BIT_CLOCK
AC97_001_P2