Layout Notes - Intel PXA27 Series Design Manual

SSP Port Interface
Figure 8-4. Internal Clock Enable Configuration Scheme Block Diagram
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8.4

Layout Notes

The tested maximum switching speed of the SSPs is 13 MHz. Design constraints at this speed are
generally not very strict. However, SSP configurations normally have one clock source switching
at the master clock frequency (a second source is also possible), plus the two data lines switching at
half that frequency, increasing the possibility of crosstalk between signals.
To ensure the most reliable design possible follow these recommendations when routing signals:
•
Keep all signal traces as short as possible.
•
Separate the signals as far as possible when routing.
•
Minimize running clock and data signals in parallel to each other.
•
Route clocks with as much of the trace on inner signal layer as possible.
SSPFRM and SSPCLKEN have slower switching frequencies and are routed with fewer
restrictions. However, for optimal system operation follow all recommendations for the clock and
data signals of the SSP.
II:8-6
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Intel PXA27x
Processor
SSPSFRM
SSPRXD
SSP2
SSPTXD
SSP2SCLK
tx_not_empty2
SSP2SCLK
SSPSFRM
SSP1
SSPRXD
SSPTXD
Peripheral SSP #2
Peripheral SSP #1
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Intel PXA27x Processor Family Design Guide