Intel PXA27 Series Design Manual page 259

D.7 LCD Controller
The LCD controllers in the PXA27x processor and PXA25x processor are similar with these
exceptions:
•
Features added to the PXA27x processor memory controller:
— Support for these Display modes:
◆
◆
◆
◆
— Larger output FIFOs (64-entry by 24 bits)
— Three 256-entry by 25-bits internal color-palette RAMs (one for each overlay and Base)
programmable to be automatically loaded at the beginning of each frame
— Command data RAM (16 x 9 bits) to hold command data
— Additional support for pixel depths of 18, 19, 24 and 25 bpp RGB formats
— No direct support for 12 bpp RGB format (indirectly supported)
— One base layer plus two overlays for single-panel displays; maximum size of each overlay
is equal the display size
— Programmable transparency for overlays
— Integrated seven-channel DMA (one channel for base plane, one channel for Overlay 1
and three channels for Overlay 2, one channel for the hardware cursor, and one channel
for the command data)
— Hardware support for color-space conversion from YCbCr to RGB for video streams
— Support for hardware cursor for single-panel display
— Programmable pixel clock from 48.75 MHz to 50.8 KHz (97.5 MHz/2 to 26 MHz/512)
— Six 16 x 64-bit Input FIFOs: one for base channel, one for Overlay 1, three for Overlay 2,
and one for the hardware cursor; one 4 x 52-bit Input FIFO for Command data for panels
with internal Frame buffer
— Four additional pins
•
Changes to the registers within the PXA25x processor memory controller were required to
support the new features and removal of support for the PXA27x processor LCD controller:
— LCCR0 expanded capabilities for command functions.
— LCCR3 expanded for number of bits per pixel and palette format capabilities.
— LCCR4 register has been added to support transparency control and palette data formats.
— LCCR5 register has been added to support interrupts for the new overlays.
— OVL1C1, OVL1C2, OVL2C1 and OVL2C2 registers added to support overlays.
— CCR register has been added to support cursor.
— CMDCR register has been added to support frame buffer panels.
®
Intel PXA27x Processor Family Design Guide
®
Intel PXA27x Processor and Intel
Up to 16777216 colors (24 bits) in active color mode
A total of 16777216 colors (24 bits) in passive color mode
Up to 24-bit per pixel single-panel color displays
LCD panel with internal Frame buffer
®
PXA25x Processor Differences
D-5