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6.2
Signals
See
Table 6-2
Table 6-2. PXA27x Processor Memory Controller I/O Signals (Sheet 1 of 2)
Signal Name
MD<31:0>
MA<25:0>
DQM<3:0>
SDCLK<2:0>
SDCKE
nSDRAS
nSDCAS
nSDCS<3:0>
nCS<5:0>
nWE
nOE
RDnWR
1
RDY
BOOT_SEL<0>
®
Intel
PXA27x Processor Design Guide
for the list of interface signals from the entire external memory controller.
Direction
Polarity
Shared PXA27x Processor Memory Controller I/O Signals
Bidirectional
NA
Output
NA
Output
Active High
SDRAM and Static Memory I/O Signals
Output
Active High
Output
Active High
Output
Active Low
Output
Active Low
1
Output
Active Low
1
Output
Active Low
Output
Active Low
Output
Active Low
Output
Active High
Input
Active High
Tied at board
Input
level
Bidirectional data for all memory types
During reads from 16-bit memory devices, the upper 16
data bits are internally pulled low.
Output address to all memory types
Data byte mask control
DQM<0> corresponds to MD<7:0>
DQM<1> corresponds to MD<15:8>
DQM<2> corresponds to MD<23:16>
DQM<3> corresponds to MD<31:24>
0 = Do not mask out corresponding byte
1 = Mask out corresponding byte
Output clocks to clock external memory
SDCLK0 is for synchronous flash memory
SDCLK1 is for SDRAM partitions 0 and 1
SDCLK2 is for SDRAM partitions 2 and 3
Output clock enable signals for external memory
SDCKE is for all SDRAM memory partitions
Row address for SDRAM
Column strobe for SDRAM
Also, nADV (address strobe) for synchronous flash
Chips selects for SDRAM
Chip selects for static memory
Write enable for SDRAM and static memory
Output enable for static memory
Miscellaneous I/O Signals
Data direction signal to be used by output transceivers
0 = MD<31:0> is driven by the PXA27x processor
1 = MD<31:0> is not driven by the PXA27x processor
Variable Latency I/O signal for inserting wait states
0 = Wait
1 = VLIO is ready
Boot Select signals – indicates the type of boot memory the
system has
0 = 32-bit ROM/flash
1 = 16-bit ROM/flash
System Memory Interface
Description
II:6-3
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