Signals; Ssp Serial Port I/O Signals - Intel PXA27 Series Design Manual

SSP Port Interface
8.2

Signals

See Table 8-1
signals for the three SSPs is separately described due to slight differences in some of the signals.
These signals are available on the GPIO pins. The GPIO must be correctly enabled in order to have
access to the functionality of the SSPs described in
Function table in the GPIO chapter of the Intel
the GPIO assignments of the SSP signals.
Table 8-1. SSP Serial Port I/O Signals (Sheet 1 of 2)
Name
SSPSCLK
SSPSYSCLK
SSPSFRM
SSPTXD
SSPRXD
SSPEXTCLK
SSPSCLKEN
SSPSCLK2
SSPSYSCLK2
SSPSFRM2
SSPTXD2
SSPRXD2
SSPEXTCLK2
II:8-2
for description of the signals associated with each of the three SSPs. Each of the
Direction
SSPSCLK is the serial bit clock used to control the timing of a
transfer. SSPSCLK is generated internally (master mode) or is
Inout
supplied externally (slave mode) as indicated by
SSCR1_1[SCLKDIR].
SSPSYSCLK is four times the SSPSCLK1 value when using Audio
Output Clock PLL Select (SSACD_1[ACPS]) and Audio Clock Divider
(SSACD_1[ACDS]).
SSPSFRM, the serial frame indicator, determines the beginning
and the end of a serialized data word. SSPSFRM is generated
Inout
internally (master mode) or is supplied externally (slave mode) as
indicated by SSPCR1_1[SFRMDIR].
Output SSPTXD is the transmit data (serial data out) serialized data line.
Input SSPRXD is the receive data (serial data in) serialized data line.
SSPEXTCLK is an external clock that is selected to replace the
internal 13-MHz clock. SSPEXTCLK is multiplexed with the
Input
SSPSCLKEN alternate function (refer to
Purpose I/O
SSPSCLKEN is an asynchronous external enable for SSPSCLK.
Input SSPSCLKEN is multiplexed with the SSPEXTCLK alternate
function (refer to
SSPSCLK2 is the serial bit clock used to control the timing of a
transfer. SSPSCLK2 is generated internally (master mode) or is
Inout
supplied externally (slave mode) as indicated by
SSCR1_1[SCLKDIR].
SSPSYSCLK2 is four times the SSPSCLK2 value when using
Output Audio Clock PLL Select (SSACD_2[ACPS]) and Audio Clock
Divider (SSACD_2[ACDS]).
SSPSFRM2, the serial frame indicator, determines the beginning
and the end of a serialized data word. SSPSFRM2 is generated
Inout
internally (master mode) or is supplied externally (slave mode) as
indicated by SSPCR1_2[SFRMDIR].
Output SSPTXD2 is the transmit data (serial data out) serialized data line.
Input SSPRXD2 is the receive data (serial data in) serialized data line.
SSPEXTCLK2 is an external clock that is selected to replace the
internal 13-MHz clock. SSPEXTCLK2 is multiplexed with the
Input
SSPSCLK2EN alternate function (refer to
Purpose I/O
Table 8-1. Refer to the GPIO Alternate
®
PXA27x Processor Family Developers Manual for
Description
Controller").
Chapter 24, "General-Purpose I/O
Controller").
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Intel PXA27x Processor Family Design Guide
Chapter 24, "General-
Controller").
Chapter 24, "General-