Feature List; Signals - Intel PXA27 Series Design Manual

Intel® Quick Capture Technology
27.2

Feature List

The functions of the quick capture interface:
•
Acquiring both data and control signals from a camera image sensor
•
Formatting of the data appropriately prior to being routed to memory through DMA
The features of the quick capture interface include:
•
Parallel interface support for 8, 9, and 10 bits
•
Serial interface support for 4-bit and 5-bit data bus connections
•
Support for ITU-R BT.656 Start-of-Active-View (SAV) and End-of-Active View (EAV)
embedded signaling
•
Pre-processed capture modes, such as RGB and YCbCr
•
Raw capture modes, such as RGGB and CMYG
•
Programmable vertical & horizontal resolutions up to 2048 x 2048
•
Two 8-entry (by 64-bit) and one 16-entry (by 64-bit) FIFOs
•
Programmable sensor clock output from 196.777 KHz to 52 MHz
•
Programmable interface timing signals for both internal and external synchronization
•
Programmable interrupts for FIFO overflow, End-of-Line (EOL), and End-of-Frame (EOF)
27.3

Signals

See Table 27-1
Table 27-1. Signal Descriptions for Quick Capture Technology
Signal Name
CIF_DD[9:0]
CIF_MCLK
CIF_PCLK
CIF_LV
CIF_FV
Any additional interface requirements are typically met through the use of standard GPIOs. A
couple of common examples are "sensor reset" or "sensor power-down ."
In addition to the data and data control signals, there is usually a separate interface for
programming the image sensor. The most common interface used for programming and control is
2
I C.
II: 27-2
for the list of signals used by the quick capture interface.
Type
Input Data lines to transmit 4,5,6,7,8,9 or 10 bits at a time
Output Programmable output clock used by the camera capture sensor
Pixel clock used by the quick capture interface of the camera to clock
Input
the pixel data into the input FIFO
Line start or alternate synchronization signal used by the sensor to
I/O
signal line read-out or as an external horizontal synchronization
Frame start or alternate synchronization signal used by the sensor to
I/O
signal frame read-out or as an external vertical synchronization
Description
®
Intel PXA27x Processor Family Design Guide