Schematics / Block Diagram; Passive Monochrome Dual-Scan Display Typical Connection - Intel PXA27 Series Design Manual

LCD Interface
Table 7-5. Passive Display Pins Required (Sheet 2 of 2)
L_LCLK_A0 Line_Clock
L_FCLK_RD Frame_Clock
L_BIAS Bias
2
N/A Vcon
NOTES:
1. "Pin Type" is in reference to the PXA27x processor. Therefore, outputs are pins that drive a signal from the processor to
another device.
2. Vcon is a signal external to the PXA27x processor. Please refer to
Note: Names used for "LCD Panel Pin" are representative names and do not match those on all LCD
panels. Similarly, not all signals are required for all modes of operation. Refer to the LCD panel
reference documentation for information on:
•
Specific signals required for correct LCD operation
•
Correct names of the signals used by the LCD panel manufacturer
7.5.3.2

Schematics / Block Diagram

See Figure 7-3
Figure 7-3. Passive Monochrome Dual-Scan Display Typical Connection
II:7-10
Line Clock – used by the LCD display to signal the end of a line of
Output pixels that transfers the line data from the shift register to the screen
and increment the line pointers.
Frame Clock – used by the LCD displays to signal the start of a new
Output
frame of pixels that resets the line pointers to the top of the screen.
AC bias used to signal the LCD display to switch the polarity of the
Output power supplies to the row and column axis of the screen to counteract
DC offset.
Contrast voltage – adjustable voltage input to LCD panel – external
N/A
voltage circuitry is required (no pin available on PXA27x processor).
for illustration of typical connections for a dual-scan monochrome, passive display.
LDD<0>
Top Left of "Upper Panel"
LDD<1>
LDD<2>
LDD<3>
LDD<4>
Top Left of "Lower Panel"
LDD<5>
LDD<6>
LDD<7>
L_PCLK_WR
L_LCLK_A0
L_FCLK_RD
L_BIAS
Section 7.4.1, "Contrast Voltage,"
DU_0
DU_1
DU_2
DU_3
DL_0
DL_1
DL_2
DL_3
PIXEL_CLOCK
LINE_CLOCK
FRAME_CLOCK
BIAS
®
Intel PXA27x Processor Family Design Guide
for detailed information.