Layout Notes - Intel PXA27 Series Design Manual

Interrupt Interface
25.4

Layout Notes

All GPIO input signals are received through a two-stage synchronizer to eliminate meta-stable
problems that result from clocking an asynchronous signal into a synchronous digital input.
Interrupt signals received using GPIO pins are acknowledged when the function is properly
configured and GPIO pin are asserted for greater than 154 ns (2 x 1/13 MHz) during run and idle
mode. A pulse less that 77 ns (1/13 MHz) on a GPIO pin cannot be detected, whereas a pulse with
a period between 77 ns and 154 ns is undetermined and must be avoided.
During standby mode, GPIO<15:0> signal and those signals associated with the keypad interface
are programmable to generate an interrupt after wake-up. To guarantee that the interrupt is
acknowledged after assertion of a GPIO signal wake-up event, the GPIO pin must be configured
for receiving an interrupt.
In addition, the minimum time the GPIO signal must be asserted is determined by the
PCFR[OPDE] bit:
•
If the PCFR[OPDE] bit is not set, the GPIO signal must be asserted for a minimum of 1 ms to
transition from the wake-up event to locking the PLLs.
•
If the PCFR[OPDE] bit is set, the GPIO signal must be asserted for a minimum of 7 ms to
transition from wake-up event to locking the PLLs.
Considerations must be made to avoid crosstalk caused by running signals too close to
asynchronous signals, such as interrupt signals. Induced noise as a result of an adjacent signal
causes a spurious interrupt if amplitude of the adjacent signal is great enough and it meets the setup
and hold timing requirements on both edges.
II:25-4
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Intel PXA27x Processor Family Design Guide