Intel PXA27 Series Design Manual page 12

Contents
Figures
Part I
1-1 PXA27x Processor Block Diagram .........................................................................................I: 1-2
2-1 1+6+1 uvia PCB Stackup .......................................................................................................I: 2-2
2-2 Recommended PCB Layer Assignment for an Eight-Layer PCB ...........................................I: 2-3
2-3 Recommended I/O Power Plane Layout ................................................................................I: 2-4
2-4 VF-BGA 13mm x 13mm Component Layout Placement Guide (Top View) ...........................I: 2-5
2-5 FS-CSP 14mm x 14mm Component Layout Placement Guide (Top View) ...........................I: 2-6
2-6 PBGA 23mm x 23mm Component Layout Placement Guide (Top View) ..............................I: 2-7
2-7 PCB Escape Routing for Copper-Defined Land Pads ............................................................I: 2-8
2-8 PCB Escape Routing for Copper Defined Land Pads ............................................................I: 2-9
2-9 Recommended Mobile Handset Dimensions Diagram.........................................................I: 2-11
2-10 FS-CSP (14x14) Tray Specification......................................................................................I: 2-13
2-11 PBGA (23x23) Tray Specification.........................................................................................I: 2-14
4-1 Minimal Voltage Regulator Power System Design Example ..................................................I: 4-3
Part II
3-1 Typical Battery and External Regulator Configuration...........................................................II: 3-5
4-1 Internal SRAM Block Diagram...............................................................................................II: 4-2
5-1 DMA controller Block Diagram ..............................................................................................II: 5-2
5-2 Companion Chip Using Fly-by DMA Transfer Interface ........................................................II: 5-4
5-3 Companion Chip Requesting Flow-Through DMA Transfers ................................................II: 5-5
6-1 General Memory Interface Configuration ..............................................................................II: 6-5
6-2 PXA27x Processor Memory System Bus Routing Topologies
(ExcludingSDCLK<x> and SDCAS) ......................................................................................II: 6-7
6-3 PXA27x Processor Memory Clock and SDCAS Routing Topology.......................................II: 6-8
6-4 Minimum Board Stack-up Configuration used for Signal Integrity .........................................II: 6-8
6-5 SDRAM Memory System Example......................................................................................II: 6-11
6-6 Block Diagram Connecting Synchronous Flash to nCS<1:0> .............................................II: 6-16
6-7 Block Diagram Connecting ROM to nCS<0> ......................................................................II: 6-18
6-8 Block Diagram Connecting SRAM to nCS<2> ....................................................................II: 6-20
6-9 Variable Latency Interface Block Diagram ..........................................................................II: 6-23
6-10 External Logic for a One-Socket Configuration Expansion PC Card...................................II: 6-27
6-11 External Logic for a Two-Socket Configuration Expansion PC Card...................................II: 6-28
6-12 Alternate Bus Master Mode .................................................................................................II: 6-32
7-1 Passive Monochrome Single-Scan Display Typical Connection ...........................................II: 7-7
7-2 Passive Monochrome Single-Scan Double-Pixel Data Display Typical Connection .............II: 7-9
7-3 Passive Monochrome Dual-Scan Display Typical Connection ............................................II: 7-10
7-4 Passive Color Single-Scan Display Typical Connection......................................................II: 7-12
7-5 Passive Color Dual-Scan Display Typical Connection ........................................................II: 7-14
7-6 Active Color 12-bit per pixel Display Typical Connection ....................................................II: 7-16
7-7 Active Color 16-bit-per-pixel Display Typical Connection ....................................................II: 7-18
7-8 Active Color 18-bit-per pixel Display Typical Connection ....................................................II: 7-20
7-9 Active Color Display 24-bit Typical Connection ...................................................................II: 7-22
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Intel PXA27x Processor Family Design Guide