Overview .........................................................................................................................I: - Intel PXA27 Series Design Manual

System Memory Interface
The following illustrations show the logical connections necessary to support hot insertion
capability:
•
Figure 6-10, "External Logic for a One-Socket Configuration Expansion PC Card," on page II:
6-27
•
Figure 6-11, "External Logic for a Two-Socket Configuration Expansion PC Card," on
page II: 6-28
For dual-voltage support, level shifting buffers are required for all PXA27x processor input signals.
Hot insertion capability requires that each socket be electrically isolated from the other and from
the remainder of the memory system. If hot insertion capability is not required, then some of the
logic shown in the following diagrams is eliminated.
Use software to set the MECR[NOS] and MECR[CIT] bits. MECR[NOS] indicates the number of
sockets that the system supports, while MECR[CIT] is written when the Card is in place. Input pins
nPWAIT and nIOIS16 are three-stated until card detect (CD) signal is asserted. To achieve this
state, software programs the MECR[CIT] bit when a card is detected. If the MECR[CIT] is 0, the
nPWAIT and nIOIS16 inputs are ignored.
Note: If the system design incorporates PCMCIA interface, LCD and MSL (Baseband Interface), refer to
Part II: Section 16.1, "Overview,"
simultaneously.
II:6-24
for important information on using these interfaces
®
Intel PXA27x Processor Design Guide