Fs-Csp Escape Routing - Intel PXA27 Series Design Manual

2.2.3.2

FS-CSP Escape Routing

This section documents the method of FS-CSP routing along with the recommended dimensions.
Table 2-3. PCB Dimensions for Copper Defined Land Pads
A: Land Pad Size
B: Solder Mask Opening
C: Typical Trace Width
D: Typical Spaces
E: Trace Width (2 Traces)
F: Spaces (2 Traces)
G: Max PTH Via Pad
H: Max PTH Via Drill Size
I: Typical Micro Via (Via-in-Pad) Drill Size
NOTE: All dimensions are in mm (inches).
On the four inner rows of the FS-CSP, route down the signals from the top layer to the inner PCB
layers for routing away from the package. See
using the FS-CSP method.
Figure 2-8. PCB Escape Routing for Copper Defined Land Pads
®
Intel PXA27x Processor Family Design Guide
Feature
Top View
Side View
PCB Design Guidelines
.65 mm BGA
.30 (.012)
.432 (.017)
.100 (.004)
.127 (.005)
.070 (.00275)
.070 (.00275)
.457 (.018)
.25 (.008)
.127 (.005)
Figure 2-7 for illustration of the PCB escape routing
A: Land Pad Size
B: Solder Mask Opening
C: Typical Trace Width
D: Typical Spaces
E: Trace Width (2 traces)
F: Spaces (2 traces)
G: Max Via Capture Pad
H: Max Via Drill Size
I: Typical Micro Via
(Via-in-Pad) Drill Size
Land Pad Land Pad
Solder Mask Solder Mask
I:2-9