Intel PXA27 Series Design Manual page 72

System Memory Interface
Table 6-2. PXA27x Processor Memory Controller I/O Signals (Sheet 2 of 2)
Signal Name
1
MBREQ
1
MBGNT
nPCE<2:1>
1
nPREG
1
nPIOR
1
nPIOW
1
nPWE
1
nPOE
1
nIOIS16
1
nPWAIT
PSKTSEL
NOTE:
1. The alternate function of the signal must be programmed to be accessed external of the PXA27x
processor. Refer to the Intel
alternate function.
II:6-4
Direction Polarity
Alternate Bus Master Mode I/O Signals
Input Active High
Output Active High
1
Output Active Low
Output NA
Output Active Low
Output Active Low
Output Active Low
Output Active Low
Input Active Low
Input Active Low
1
Output NA
®
PXA27x Processor Family Developers Manual on how to configure the
Alternate bus master request
Alternate bus master grant
Card Interface I/O Signals
Byte lane enables for the card interface. nPCE1 enables
byte MD<7:0>; nPCE2 enables byte MD<15:8>
Serves as the card interface address bit <26> and selects
register space (I/O or attribute) versus memory space
Card interface I/O space output enable
Card interface I/O space write enable
Card interface attribute and common memory space Write
enable
Also, write enable for variable latency I/O memory
Card interface attribute and common memory space output
enable
Card interface input from I/O space telling size of data bus
0 = 16-bit I/O space
1 = 8-bit I/O space
Card interface input for inserting wait states
0 – Wait
1 – Card is ready
In a single socket solution, this is the active low output
enable used as the nOE for the data transceivers.
In a dual socket solution, the socket select
0 – Socket 0
1 – Socket 1
®
Intel PXA27x Processor Design Guide
Description