External Clock Source Configuration Scheme - Intel PXA27 Series Design Manual

SSP Port Interface
Figure 8-1. Standard SSP Configuration Scheme Block Diagram
8.3.2

External Clock Source Configuration Scheme

The external clock source configuration allows for an external clock source to be the SSPCLK
generation source. Using an external clock source is different than the SSPSCLK operating as a
slave. When using an external clock source, the SSPSCLK is still a master; however, the external
clock replaces the internal 13 MHz clock as the source for the SSPSCLK generation.
The external clock source configuration allows SSPSCLK frequencies with bases other than
13 MHz, or for using a network clock to serve as a clock source for an SSP, but the SSP is still the
master of SSPSCLK.
See Figure 8-2
configuration.
Figure 8-2. External Clock Source Configuration Scheme Block Diagram
II:8-4
®
Intel PXA27x Processor
for illustration of the physical connection of the external clock source
®
Intel PXA27x Processor
SSPSCLK
SSPSFRM
SSPRXD
SSPTXD
SSPCLKEN/
SSPEXTCLK
SSPSCLK
SSPSFRM
SSPRXD
SSPTXD
SSPEXTCLK
Other SSP
or Network
clock source
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Intel PXA27x Processor Family Design Guide
Peripheral SSP
Peripheral SSP